This application claims the benefit of a Japanese Patent Application No. 2001-322811 filed Oct. 19, 2001 in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to jigs for semiconductor substrates and methods for manufacturing semiconductor devices using the same, and more particularly to a method of manufacturing a semiconductor device including a step of back grinding the back surface of the semiconductor substrate (wafer), a step of dicing for singularizing into semiconductor elements, and a step of bonding including picking up such singularized semiconductor elements and mounting them to the mounting device; as well as to a jig for semiconductor devices used for such a method.
Recently, with the necessity for semiconductor packages to be light, thin, short and small, the related wafers are also becoming thinner.
In each step such as in the back grind step, when the thickness of the wafer is less than 100 μm, the wafer transportation and the semiconductor manufacturing process are technically very difficult using conventional methods. For this reason, a method of securely transporting and performing the process of semiconductor manufacturing with thinner wafers is desired.
2. Description of the Related Art
Conventionally, in manufacturing steps consisting of back grinding the semiconductor substrate (hereinafter also referred to as the wafer), singularizing the wafer into semiconductor elements by dicing, and bonding the singularized semiconductor elements on, for example, the mounting substrate, the transportation and the predetermined processes are carried out with the wafer attached to a tape. Each manufacturing step is described with reference to FIG. 1.
First, as shown in FIG. 1A, a circuit-forming surface is attached to a protection tape 2 (attachment step). Subsequently, as shown in FIG. 1B, the wafer 1 is installed to a chuck table 4 and the back surface of the wafer 1 is back grounded by a rotating grind whetstone 3 (back grind step). As a result, the wafer 1 is thinned.
Secondly, a die attach film (not shown) is attached to the back surface of the thinned wafer 1 (die attach mount step).
Subsequently, as shown in FIG. 1C, as the protection tape 2 attached to the wafer 1 is peeled, the back surface of the wafer 1 is attached to a dicing tape 6 (tape reapplication step). The dicing tape 6 is previously arranged in a frame 5 having a shape of a frame.
Next, as shown in FIG. 1D, the wafer 1 is cut along the predetermined dicing line using a dicing saw 7, and the wafer is singularized into semiconductor elements 10 (singularization step).
The singularized semiconductor elements 10 are pressed on their back surfaces through the dicing tape 6 using a push up pin 11 and as a result, the semiconductor elements 10 are peeled from the dicing tape 6, as shown in FIG. 1E. A collet 8 is located opposite the push up pin 11 on the upper side, and the peeled semiconductor elements 10 are adsorbed to and held by the collet 8 (pick up step).
The semiconductor elements 10 held by the collet 8 are transferred to the mounting substrate 9 as the collet 8 moves, and are bonded to the predetermined position on the mounting substrate 9 by the die attach film (bonding step). Through these steps, the semiconductor elements 10 formed on the wafer 1 are thinned and singularized, and then mounted on the mounting substrate 9.
The wafer 1 made extremely thin by the back grind step warps, which was not a problem with a conventional thickness. The thinning of the wafer 1 is not only the direct cause of reduction in the absolute strength of the wafer. When the wafer 1 warps, the performance of each manufacturing step after the back grind step is degraded, and along with transportation of the wafer becomes a factor of breakage failure.
This is significant particularly in the tape reapplication step. In other words, during the tape application, bubbles are likely to enter between the wafer 1 and the dicing tape 6 if the wafer 1 is thin.
When bubbles enter, the wafer 1 and the dicing tape 6 do not adhere at the locations where bubbles exist, and thus the adhesive strength between the wafer 1 and the dicing tape 6 decreases. Furthermore, when heat is applied, the bubbles expand and the wafer 1 and the dicing tape 6 are further separated from each other. Therefore, when bubbles enter, there is a possibility that an appropriate process may not be successfully performed in the steps subsequently conducted (for example, the singularization step), and the yield of the semiconductor manufacturing process is lowered, and in the worst case, the wafer 1 may break due to the expansion of bubbles.
On the other hand, in considering peeling the protection tape, the wafer 1 may break when the protection tape 2 is being peeled, or the wafer 1 may be peeled from the periphery at the start of peeling, and then break.